Publications
My research sits at the intersection of computer architecture security and microarchitectural performance, with a focus on how aggressive front-end optimizations in modern processors interact with security boundaries. I study both how these optimizations create exploitable timing side channels, and how speculative techniques can be harnessed to improve processor efficiency.
55th International Symposium on Microarchitecture (MICRO) · 2022
Logan Moody, Wei Qi, Rasool Sharifi, Layne Berry, Joey Rudek, Jayesh Gaur, Jeff Parkhurst, Sreenivas Subramoney, Kevin Skadron, Ashish Venkat
Modern processors frequently execute micro-operations (µops) whose results are never consumed—dead µops that waste execution resources without contributing to program output. We propose Speculative Code Compaction (SCC), a microarchitectural technique that speculatively identifies and eliminates dead µops using dynamic dataflow analysis. SCC reduces back-end pressure and improves instruction throughput transparently to software, achieving meaningful speedups across a range of real-world workloads.
48th International Symposium on Computer Architecture (ISCA) · 2021
Xida Ren, Logan Moody, Mohammadkazem Taram, Matthew Jordan, Dean M. Tullsen, Ashish Venkat
Modern processors cache decoded micro-operations (µops) in a µop cache to skip redundant instruction fetch and decode. We show that the µop cache introduces a timing side channel that can be exploited by a malicious actor to leak sensitive information across security boundaries. We demonstrate end-to-end Spectre-style attacks on Intel and AMD processors—leaking data across process and VM boundaries—and evaluate potential hardware and software mitigations.
